The present invention relates to a semiconductor integrated circuit having a low power consumption mode accompanying power supply/interruption control. More particularly, the invention relates to a technique effectively applied to a microcomputer having a plurality of power regions in each of which operation power can be supplied/interrupted.
Many microcomputers have the function of changing a program execution state to a low-power-consumption state for the purpose of reducing power consumption. The low-power-consumption states include a CPU sleep mode, an entire-module stop mode, a software standby mode, and a hardware standby mode. In each of the modes, the operation of an internal circuit is stopped by stopping supply of clocks to modules and stopping an oscillator, and a standby mode is set, thereby realizing reduction in power consumption.
On the other hand, in a process of manufacturing a semiconductor integrated circuit, as a circuit device is becoming finer, the operation power voltage is becoming lower as the withstand voltage of a transistor decreases. Accordingly, there is a tendency that the gate threshold voltage of a MOS transistor is also lowered. Since the lower operation voltage and lower threshold voltage are desirable for reduction in power consumption and increase in operation speed, a voltage obtained by decreasing an external power supply voltage tends to be used as an operation power. However, decrease in the threshold voltage causes increase in leak current such as a sub-threshold leak current of a MOS transistor, and standby current in the low-power-consumption state increases because power supply voltage is not interrupted.
Consequently, a circuit system of reducing the standby current by interrupting (stopping) supply of the operation power to a part or all of inner circuits at the time of transition to the low-power-consumption state can be employed. For example, in a predetermined low-power-consumption mode such as a software standby mode, the power supply of an internal ROM requiring no power supply is interrupted. In a predetermined low-power-consumption mode such as a deep standby mode, the operation power supply to all or part of internal logics such as a CPU in addition to the internal ROM is interrupted. Further, in the case where data in a RAM does not have to be held, the operation power of the RAM can be also interrupted.
A reset instruction and an interruption request for a microcomputer are factors of cancelling the low-power-consumption state. Since the cancellation factors are generated asynchronously with the microcomputer, when the operation is interrupted by a reset (initialization) instruction or an interruption request during transition to the low-power-consumption state, there is the possibility that the power supply interrupting sequence is interrupted and undesirable operation is performed. For example, in the case of interrupting the power supply by cutting off a clamp MOS transistor and discharging an output of the clamp MOS transistor to the ground in a power supply circuit for generating an operation voltage decreased by negative feedback control of the clamp MOS transistor, if an initialization instruction is given during the power supply interrupting sequence, the discharging is performed in a state where the cutoff of the clamp MOS transistor is incomplete, and a flow-through current is generated in the power supply circuit. Depending on a low-power-consumption state which is set, when the power supply interruption is cancelled in response to a reset instruction, there is the possibility that an unstable signal is supplied to a circuit and erroneous operation or data destruction occurs. For example, when an inconstant propagation preventing circuit is made inactive before the power supply interruption is cancelled, and the power supply interruption is cancelled, at that instance, an unstable signal is supplied to the circuit, and an erroneous operation or data destruction occurs.
Japanese Unexamined Patent Publication No. Hei 9(1997)-069052 relates to a technique of controlling reception of the asynchronous cancellation factors such as an interruption for cancelling the power supply interruption state. The publication describes that, in a device (such as a DMAC, CPU, or the like) having a plurality of low-power-consumption operation modes for reducing current consumption, an interruption is inhibited in a period of transition to the low-power-consumption mode and a predetermined period after shift to the low-power-consumption mode. After lapse of the period, an interruption is permitted. Japanese Unexamined Patent Publication No. 2003-316486 describes that a power consumption reduction circuit is provided with delay means by which cancellation of clamping of a reset signal to a power supply controllable circuit becomes the last at the time of restarting power supply.